Programmable circuits (e.g., field-programmable gate array (FPGA) devices) include logic blocks, generic structures and input-output structures that can be configured to perform any of a variety of functions and support different protocols. For instance, input-output elements on a programmable device may be configurable to support different input-output standards.
Generally, an input-output buffer circuit on a programmable device may support both high-speed single-ended memory standards, such as stub series terminated logic (SSTL), high-speed transceiver logic (HSTL), etc., and differential memory standards, such as low voltage differential signaling (LVDS), etc. For example, a pair of output buffers may be coupled such that they may be configured as either two separate single-ended output buffers or a pair of differential output buffers.
However, in order to fully support different memory interfaces, input-output buffers also need to be able to support high data rate memory transfers. Pin capacitance must be kept substantially low in order to support the ever increasing memory interface performance. For instance, high speed memory devices such as double data rate type 3 (DDR3) and DDR4 devices generally have a relatively low pin capacitance that ranges from 1.5 pF (picofarad) to 2 pF.
The programmable device that is used as a memory controller on the other hand, may generally have a much higher pin capacitance. As a result, the memory controller (i.e., the programmable device) may have an output slew rate that is substantially lower than that of a DDR memory device.
Therefore, even though input-output buffers on a programmable device may be able to support different memory standards, the lower output slew rates may create a potentially performance limiting bottleneck for high data rate memory interfaces.